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LTC1267 LTC1267-ADJ/LTC1267-ADJ5 Dual High Efficiency Synchronous Step-Down Switching Regulators
FEATURES
s s s s s
DESCRIPTIO
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Dual Outputs: 3.3V and 5V, Two Adjustables or Adjustable and 5V Wide VIN Range: 4V to 40V Ultra-High Efficiency: Up to 95% Low Supply Current in Shutdown: 20A Current Mode Operation for Excellent Line and Load Transient Response High Efficiency Maintained Over a Wide Output Current Range Independent Micropower Shutdown Very Low Dropout Operation: 100% Duty Cycle Synchronous FET Switching for High Efficiency Available in Standard 28-Pin SSOP
The LTC(R)1267 series are dual synchronous step-down switching regulator controllers featuring automatic Burst ModeTM operation to maintain high efficiencies at low output currents. The LTC1267 is composed of two separate regulator blocks, each driving a pair of external complementary power MOSFETs at switching frequencies up to 400kHz. The LTC1267 uses a constant off-time currentmode architecture to provide constant ripple current in the inductor and provide excellent line and load transient response. A separate pin and on-board switch allow the MOSFET driver power to be derived from the regulated output voltage, providing significant efficiency improvement when operating at high input voltage. The output current level is user-programmable via an external current sense resistor. The LTC1267 series is ideal for applications requiring dual output voltages with high conversion efficiencies over a wide load current range in a small amount of board space.
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a trademark of Linear Technology Corporation.
APPLICATI
s s s s
S
Notebook and Palmtop Computers Battery-Operated Digital Devices Portable Instruments DC Power Distribution Systems
TYPICAL APPLICATI
+
CIN3 100F 50V
VIN 5.4V to 25V
+
3.3F P-CH Si9435DY 1N4148 8 4 5 14 1000pF 13 12 SENSE - 3 SHDN3 NGATE 3 VCC3 PGATE 3 PDRIVE 3 SENSE + 3
0.15F 3 CAP3 1 VCC 2 VIN
0.15F 1N4148 27 26 28 21 0.1F P-CH Si9435DY
VOUT3 3.3V 2A
RSENSE3 0.05
L3 20H
0.1F
D3 MBRS140T3
6 N-CH Si9410DY
MSHDN CAP5 EXT VCC VCC5 25 PGATE 5 24 PDRIVE 5 18 + SENSE 5 LTC1267 17 SENSE - 5 19 SHDN5 23 NGATE 5 ITH5 15 CT5 16 SGND5 PGND5 20 22
+
COUT3 220F 10V x2
PGND3 SGND3 CT3 7 11 9
ITH3 10
N-CH Si9410DY
CC3 CC5 CT5 CT3 270pF 3300pF 3300pF 270pF RSENSE3: KRL SL-1R050J L3: COILTRONICS CTX20-4 RC3 1k RC5 1k RSENSE5: KRL SL-1R050J L5: COILTRONICS CTX33-4
LTC1267 * F01
SHDN3, SHDN5, MSHDN 0V = NORMAL, >2V = SHDN
Figure 1. High Efficiency Dual 3.3V, 5V
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+ +
3.3F CIN5 100F 50V L5 33H RSENSE5 0.05 VOUT5 5V 2A 1000pF D5 MBRS140T3
UO
UO
+
COUT5 220F 10V x2
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LTC1267 LTC1267-ADJ/LTC1267-ADJ5 ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW VCC 1 VIN 2 CAP3 3 PGATE 3 4 PDRIVE 3 5 NGATE 3 6 PGND3 7 VCC3 8 CT3 9 ITH3 10 SGND3 11 SHDN3 12 SENSE - 3 13 SENSE + 3 14 28 EXT VCC 27 MSHDN 26 CAP5 25 PGATE 5 24 PDRIVE 5 23 NGATE 5 22 PGND5 21 VCC5 20 SGND5 19 SHDN5 18 SENSE + 5 17 SENSE - 5 16 CT5 15 ITH5
Input Supply Voltage (Pin 2)..................... - 0.3V to 40V VCC Output Current (Pin 1) .................................. 50mA EXT VCC Input Voltage (Pin 28) .............................. 10V Continuous Output Current (Pins 5, 6, 23, 24) .... 50mA Sense Voltages LTC1267 (Pins 13, 14, 17, 18) ............. VCC to - 0.3V LTC1267-ADJ (Pins 12, 13, 17, 18) ..... VCC to - 0.3V LTC1267-ADJ5 (Pins 12, 13, 17, 18) ... VCC to - 0.3V Shutdown Voltages LTC1267 (Pins 12, 19, 27) ................................... 7V LTC1267-ADJ (Pins 11, 27) ................................. 7V LTC1267-ADJ5 (Pins 11, 19, 27) ......................... 7V Operating Ambient Temperature Range ...... 0C to 70C Extended Commercial Temperature Range ........................... - 40C to 85C Junction Temperature (Note 1) ............................ 125C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
TOP VIEW VCC 1 VIN 2 CAP1 3 PGATE 1 4 PDRIVE 1 5 NGATE 1 6 VCC1 7 CT1 8 ITH1 9 SGND1 10 SHDN1 11 SENSE - 1 12 SENSE + 1 13 VFB1 14 28 EXT VCC 27 MSHDN 26 CAP2 25 PGATE 2 24 PDRIVE 2 23 NGATE 2 22 PGND 21 VCC2 20 SGND2 19 VFB2 18 SENSE + 2 17 SENSE - 2 16 CT2 15 ITH2
ORDER PART NUMBER LTC1267CG
G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125C, JA = 95C/W
ORDER PART NUMBER LTC1267CG-ADJ
TOP VIEW VCC 1 VIN 2 CAP1 3 PGATE 1 4 PDRIVE 1 5 NGATE 1 6 VCC1 7 CT1 8 ITH1 9 SGND1 10 SHDN1 11 SENSE - 1 12 SENSE + 1 13 VFB1 14 28 EXT VCC 27 MSHDN 26 CAP5 25 PGATE 5 24 PDRIVE 5 23 NGATE 5 22 PGND 21 VCC5 20 SGND5 19 SHDN5 18 SENSE + 5 17 SENSE - 5 16 CT5 15 ITH5
ORDER PART NUMBER LTC1267CG-ADJ5
G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125C, JA = 95C/W
G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125C, JA = 95C/W
Consult factory for Industrial and Military grade parts. The LTC1267 demo circuit board is now available. Consult factory.
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LTC1267 LTC1267-ADJ/LTC1267-ADJ5
ELECTRICAL CHARACTERISTICS
TA = 25C, VIN = 12V, VMSHDN, VSHDN1,3,5 = 0V (Note 2), unless otherwise noted.
SYMBOL VFB1, 2 IFB1, 2 VOUT PARAMETER Feedback Voltage Feedback Current Regulated Output Voltage 3.3V Output 5V Output Output Voltage Line Regulation Output Voltage Load Regulation 3.3V Output 5V Output Burst Mode Output Ripple VCC VIN - VCC IEXTVCC IIN Internal Regulator Voltage VCC Dropout Voltage EXT VCC Pin Current (Note 3) VIN Pin Current (Note 3) Normal Shutdown VEXTVCC - VCC VPGATE - VIN EXT VCC Switch Drop PGate to Source Voltage (Off) CONDITIONS LTC1267-ADJ, LTC1267-ADJ5: VIN = 9V LTC1267-ADJ, LTC1267-ADJ5 LTC1267: VIN = 9V, ILOAD = 700mA LTC1267, LTC1267-ADJ5: VIN = 9V, ILOAD = 700mA VIN = 9V to 40V Figure 1 Circuit 5mA < ILOAD < 2.0A 5mA < ILOAD < 2.0A ILOAD = 0A VIN = 12V to 40V, EXT VCC = 0V, ICC = 10mA VIN = 4V, EXT VCC = Open, ICC = 10mA EXT VCC = 5V, Sleep Mode VIN = 12V, EXT VCC = 5V VIN = 40V, EXT VCC = 5V VIN = 12V, VMSHDN = 2V VIN = 40V, VMSHDN = 2V VIN = 12V, EXT VCC = 5V, ISWITCH = 10mA VIN = 12V VIN = 40V LTC1267-ADJ, LTC1267-ADJ5 VSENSE -1, 2 = 5.1V, VFB1, 2 = VOUT/4 + 25mV (Forced) VSENSE - 1, 2 = 4.9V, VFB1, 2 = VOUT/4 - 25mV (Forced) LTC1267 VSENSE - 3, 5 = VOUT + 100mV (Forced) VSENSE - 3, 5 = VOUT - 100mV (Forced) - 0.2 - 0.2
q q q q q q q
MIN 1.21
TYP 1.25 0.2
MAX 1.29 1 3.43 5.20 40 65 100 4.75 300
UNITS V A V V mV mV mV mVP-P V mV A A A A A
3.23 4.90 - 40
3.33 5.05 0 40 60 50
VOUT
4.25
4.5 200 360 320 550 15 25 200 0 0 25 160 25 160 1.4 0.8 12 70 2 5 100
300
mV V V mV mV mV mV V V A A A s ns
VSENSE +1, 2 - Current Sense Threshold Voltage VSENSE -1, 2 VSENSE + 3, 5 - Current Sense Threshold Voltage VSENSE -3, 5 VSHDN Shutdown Threshold MSHDN SHDN1, 3, 5 MSHDN Input Current CT Pin Discharge Current Off-Time (Note 4) Driver Output Transition Times
q
135
180
q
135 0.8 0.6
180 2.0 2.0 20 90 10 6 200
IMSHDN ICT tOFF tr, tf
VMSHDN = 5V VOUT in Regulation VOUT = 0V CT = 390pF, ILOAD = 700mA, VIN = 10V CL = 3000pF (PDrive and NGate Pins), VIN = 6V 50 4
3
LTC1267 LTC1267-ADJ/LTC1267-ADJ5
ELECTRICAL CHARACTERISTICS
SYMBOL VFB1, 2 VOUT PARAMETER Feedback Voltage Regulated Output Voltage 3.3V Output 5V Output VIN Pin Current (Note 3) Normal Shutdown IEXTVCC VCC VSENSE + - VSENSE - VMSHDN tOFF EXT VCC Pin Current (Note 3) Internal Regulator Voltage Current Sense Threshold Voltage Shutdown Threshold MSHDN Off-Time (Note 4) CONDITIONS
- 40C TA 85C, VIN = 12V, VMSHDN, VSHDN1,3,5 = 0V (Notes 2, 5), unless otherwise noted.
MIN 1.2 3.17 4.85 TYP 1.25 3.30 5.05 320 550 15 25 360 4.5 130 0.8 CT = 390pF, ILOAD = 700mA, VIN = 10V 3 25 160 1.4 5 185 2.0 7 MAX 1.3 3.48 5.25 UNITS V V V A A A A A V mV mV V s LTC1267-ADJ, LTC1267-ADJ5: VIN = 9V VIN = 9V ILOAD = 700mA ILOAD = 700mA VIN = 12V, EXT VCC = 5V VIN = 40V, EXT VCC = 5V VIN = 12V, VMSHDN = 2V VIN = 40V, VMSHDN = 2V EXT VCC = 5V, Sleep Mode VIN = 12V to 40V, EXT VCC = 0V, ICC = 20mA Low Threshold (Forced) High Threshold (Forced)
IIN
The q denotes specifications which apply over the full operating temperature range. Note 1: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC1267/LTC1267-ADJ/LTC1267ADJ5: TJ = TA + (PD x 95C/ W) Note 2: On LTC1267 versions which have MSHDN and SHDN1, 3, 5 pins, they must be at ground potential for testing. Note 3: The LTC1267 VIN and EXT VCC current measurements exclude MOSFET driver currents. When VCC power is derived from the output via EXT VCC, the input current increases by (IGATECHG x Duty Cycle)/Efficiency. See Typical Performance Characteristics and Applications Information.
Note 4: In applications where RSENSE is placed at ground potential, the off-time increases approximately 40%. Note 5: The LTC1267/LTC1267-ADJ/LTC1267-ADJ5 are not tested and quality-assurance sampled at - 40C to 85C. These specifications are guaranteed by design and/or correlation. Note 6: The logic level power MOSFETs shown in Figure 1 are rated for VDS(MAX) = 30V. For operation at VIN > 30V, use standard threshold MOSFETs with EXT VCC powered from a 9V supply. See applications information. Note 7: LTC1267-ADJ and LTC1267-ADJ5 are tested at an output of 3.3V
TYPICAL PERFORMANCE CHARACTERISTICS
5V Output Efficiency vs Load Current
100 95 VIN = 10V 90 90 100 95
OUTPUT VOLTAGE (mV)
EFFICIENCY (%)
85 VIN = 20V 80 75 70 65 60 0.01 0.1 1 LOAD CURRENT (A) 10
LTC1267 * G01
EFFICIENCY (%)
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UW
3.3V Output Efficiency vs Load Current
30 20
Load Regulation
VIN = 10V
10 0 -10 -20 -30 -40 -50 VIN = 10V VOUT = 5V
VIN = 20V VOUT = 3.3V VIN = 10V VOUT = 3.3V
85 VIN = 20V 80 75 70 65 60 0.01 0.1 1 LOAD CURRENT (A) 10
LTC1267 * G02
VIN = 20V VOUT = 5V
-60 0 0.5 1.5 1.0 LOAD CURRENT 2.0 2.5
LTC1267 * G03
LTC1267 LTC1267-ADJ/LTC1267-ADJ5 TYPICAL PERFORMANCE CHARACTERISTICS
5V Output Efficiency vs Line Voltage
100 95 90 LOGIC THRESHOLD GATE, 1A
EFFICIENCY (%)
OUTPUT VOLTAGE (mV)
EFFICIENCY (%)
85 80 75 70 65 60 0 5 10 LOGIC THRESHOLD GATE, 0.1A STANDARD THRESHOLD GATE, 1A VEXTVCC = 9V
STANDARD THRESHOLD GATE, 0.1A VEXTVCC = 9V 35 40
15 20 25 30 INPUT VOLTAGE (V)
Operating Frequency vs (VIN - VOUT)
2.0
NORMALIZED FREQUENCY (Hz)
VOUT = 5V ILOAD = 700mA 1.5
SENSE VOLTAGE (mV)
OFF-TIME (s)
1.0
0.5
0
0
5
15 20 10 (VIN - VOUT) VOLTAGE (V)
PI FU CTIO S
VIN: Main Supply Input Pin.
EXT VCC: External VCC Supply for the Regulators. See EXT VCC Pin Connection. VCC: Output of the Internal 4.5V Linear Regulator, EXT VCC Switch, and Supply Inputs for Driver and Control Circuits. The driver and control circuits are powered from the higher of the 4.5V regulator or EXT VCC voltage. Must be closely decoupled to the power ground. PGND: Power Ground. Connect to the source of N-channel MOSFET and the (-) terminal of CIN.
UW
NOTE 6
LTC1267 * G04
3.3V Output Efficiency vs Line Voltage
100 95 90 NOTE 6 85 LOGIC THRESHOLD GATE, 0.1A 75 STANDARD 70 THRESHOLD GATE, 1A VEXTVCC = 9V 80 65 60 0 5 10 LOGIC THRESHOLD GATE, 1A
60 40
Line Regulation
NOTE 6 20 0 -20 -40 -60
STANDARD THRESHOLD GATE, 0.1A VEXTVCC = 9V 35 40
15 20 25 30 INPUT VOLTAGE (V)
0
5
10
15 20 25 30 INPUT VOLTAGE (V)
35
40
LTC1267 * G05
LT1267 * G06
Off-Time vs Output Voltage
160
0C
180 160 140 120 100 80 60 40 20
Current Sense Threshold Voltage
140
25C 70C
120 100 80 60 3.3V OUTPUT REGULATOR 40 20
25
MAXIMUM THRESHOLD
5V OUTPUT REGULATOR
MINIMUM THRESHOLD
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT VOLTAGE (V)
LTC1267 * F08
0 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C)
LTC1267 * G09
LTC1267 * G07
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(Applies to both regulator sections)
SGND: Small-Signal Ground. Must be routed separately from other grounds to the (-) terminal of COUT. PGATE: Level Shifted Gate Drive for the Top P-channel MOSFET. The voltage swing at the PGate pin is from VIN to (VIN - VCC). PDRIVE: High Current Gate Drive for the Top P-channel MOSFET. The PDrive pin swings from VCC to GND. NGATE: High Current Drive for the Bottom N-channel MOSFET. The NGate pin swings from GND to VCC.
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LTC1267 LTC1267-ADJ/LTC1267-ADJ5
PI FU CTIO S
CAP: Charge Compensation Pin. A capacitor to VCC provides charge required by the PGate level shift capacitor during supply transitions. The charge compensation capacitor must be larger than the gate drive capacitor. CT: External Capacitor. From this pin to ground sets the operating frequency. (The frequency is also dependent upon the ratio VOUT/VIN). ITH : Gain Amplifier Decoupling Point. The regulator current comparator threshold increases with the ITH pin voltage. SENSE - : Connects to internal resistive divider which sets the output voltage. The Sense - pin is also the (-) input of the current comparator. SENSE + : The (+) Input for the Current Comparator. A built-in offset between the Sense+ and Sense- pins, in conjunction with RSENSE, sets the current trip threshold. VFB1, 2: These pins receive the feedback voltage from an external resistive divider used to set the output voltage of the adjustable section. MSHDN: Master Shutdown Pin. Taking MSHDN high shuts down VCC and all control circuitry. SHDN1, 3, 5: These pins shut down the individual regulator control circuitry (VCC is not affected). Taking SHDN1, 3, 5 pins high turns off the control circuitry of adjustable 1, 3.3V, 5V sections and holds both MOSFETs off. Must be at ground potential for normal operation.
FU CTIO AL DIAGRA
(Internal divider broken at VFB1,2 for adjustable versions. Only one regulator block shown.)
VIN MSHDN LOW DROPOUT 4.5V REGULATOR LOW DROPOUT SWITCH CAP PGATE VCC VCC 550k 550k PDRIVE SLEEP NGATE PGND V SENSE+ SENSE -
EXT VCC
+
S VTH1
R Q S
C 25mV TO 150mV VOS 13k
T
ITH
G 1.25V VFB1, 2
OFF-TIME CONTROL CT
SENSE -
SGND
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-
+
+
-
-
VTH2
-
+
-
+
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100k
REFERENCE
SHDN1, 3, 5
LTC1267 * FD
LTC1267 LTC1267-ADJ/LTC1267-ADJ5
OPERATIO
The LTC1267 series consists of two individual regulator blocks, each using current mode, constant off-time architectures to synchronously switch an external pair of complementary power MOSFETs. The two regulators are internally set to provide output voltages of 3.3V and 5V for the LTC1267. The LTC1267-ADJ is configured to provide two adjustable output voltages, each set by their individual external resistor dividers. The LTC1267-ADJ5 has adjustable and 5V output voltages. Operating frequency is individually set on each section by the external capacitors attached to the CT pin. The output voltage is sensed by an internal voltage divider connected to the Sense - pin or external divider returned to the VFB pin (LTC1267-ADJ, LTC1267-ADJ5). A voltage comparator V and a gain block G compare the divided output voltage with a reference voltage of 1.25V. To optimize efficiency, the LTC1267 series automatically switches between two modes of operation, Burst Mode and continuous mode. The voltage comparator is the primary control element when the device is in Burst Mode operation, while the gain block controls the output voltage in continuous mode. A low dropout 4.5V regulator provides the operating voltage VCC for the MOSFET drivers and control circuitry during start-up. During normal operation, the LTC1267 family powers the drivers and control from the output via the EXT VCC pin to improve efficency. The NGate pin is referenced to ground and drives the N-channel MOSFET gate directly. The P-channel gate drive must be referenced to the main supply input VIN, which is accomplished by level-shifting the PDrive signal via an internal 550k resistor and an external capacitor. During the switch "ON" cycle in continuous mode, current comparator C monitors the voltage between Sense+ and Sense- pins connected across an external shunt in series with the inductor. When the voltage across the shunt reaches its threshold value, the PGate output is switched to VIN, turning off the P-channel MOSFET. The timing capacitor CT is now allowed to discharge at a rate determined by the off-time controller. The discharge current is made proportional to the output voltage to model the inductor current, which decays at a rate that is also
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(Refer to Functional Diagram)
proportional to the output voltage. While the timing capacitor is discharging, the NGate output is high, turning on the N-channel MOSFET. When the voltage on the timing capacitor has discharged past VTH1, comparator T trips, setting the flip-flop. This causes the NGate output to go low (turning off the N-channel MOSFET) and the PGate output to also go low (turning the P-channel MOSFET back on). The cycle then repeats. As the load current increases, the output voltage decreases slightly. This causes the output of the gain stage to increase the current comparator threshold, thus tracking the load current. The sequence of events for Burst Mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. When the output voltage is at or above the desired regulated value, the P-channel MOSFET is held off by comparator V and the timing capacitor continues to discharge below VTH1. When the timing capacitor discharges past VTH2, voltage comparator S trips, causing the internal SLEEP line to go low and the N-channel MOSFET to turn off. The circuit now enters sleep mode with both power MOSFETs turned off. In sleep mode a majority of the circuitry is turned off, dropping the quiescent current from several mA (with the MOSFETs switching) to 360A. The load current is now being supplied by the output capacitor. When the output voltage has dropped by the amount of hysteresis in comparator V, the P-channel MOSFET is again turned on and this process repeats. To avoid the operation of the current loop interfering with Burst Mode operation, a built-in offset VOS is incorporated in the gain stage. This prevents the current comparator threshold from increasing until the output voltage has dropped below a minimum threshold. To prevent both the external MOSFETs from ever being turned on at the same time, feedback is incorporated to sense the state of the driver output pins. Before the NGate output can go high, the PDrive output must also be high. Likewise, the PDrive output is prevented from going low while the NGate output is high.
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LTC1267 LTC1267-ADJ/LTC1267-ADJ5
APPLICATIO S I FOR ATIO
The LTC1267 Compared to the LTC1159, LTC1149 and LTC1142 Family The LTC1267 family is a dual LTC1159. Identical to the LTC1159, the LTC1267 can reduce the quiescent and shutdown currents by making use of an internal switch which allows the driver and control sections to be powered from an external source to improve efficiency. The basic LTC1267 application circuit shown in Figure 1 is limited to a maximum input voltage of 30V due to external MOSFET breakdown. If the application does not require greater than 18V operation the LTC1142HV should be used. Component Selection The basic LTC1267 application circuit is shown in Figure 1. External component selection is driven by the load requirement and begins with the selection of RSENSE. Once RSENSE is known, CT and L can be chosen. Next, the power MOSFETs and diode are selected. Finally, CIN and COUT are selected and the loop is compensated. Since the adjustable, 3.3V and 5V sections in the LTC1267 are identical, the process of component selection is the same for both sections. RSENSE Selection for Output Current RSENSE is chosen based on the required output current. The LTC1267 current comparators have a threshold range which extends from a minimum of 25mV/RSENSE to a maximum of 150mV/RSENSE. The current comparator threshold sets the peak of the inductor ripple current, yielding a maximum output current IMAX equal to the peak value less half the peak-to-peak ripple current. For proper Burst Mode operation, IRIPPLE(P-P) must be less than or equal to the minimum current comparator threshold. Since efficiency generally increases with ripple current, the maximum allowable ripple current is assumed, i.e., IRIPPLE(P-P) = 25mV/RSENSE (see CT and L Selection for Operating Frequency). Solving for RSENSE and allowing a margin for variations in the LTC1267 and external component values yields: RSENSE = 100mV IMAX
RSENSE ()
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The LTC1267 works well with values of RSENSE from 0.02 to 0.2. Figure 2 shows the selection of RSENSE vs maximum output current.
0.20
0.15
0.10
0.05
0 0 1 3 4 2 MAXIMUM OUTPUT CURRENT (A) 5
LTC1267 * F02
Figure 2. Selecting RSENSE
The load current below which Burst Mode operation commences, IBURST and the peak short-circuit current ISC(PK) both track IMAX. Once RSENSE has been chosen, IBURST and ISC(PK) can be predicted from the following:
IBURST 15mV RSENSE ISC(PK) = 150mV RSENSE
The LTC1267 automatically extends tOFF during a short circuit to allow sufficient time for the inductor current to decay between switch cycles. The resulting ripple current causes the average short-circuit current ISC(AVG) to be reduced to approximately IMAX. CT and L Selection for Operating Frequency Each regulator section of the LTC1267 uses a constant offtime architecture with tOFF determined by an external timing capacitor CT. The value of CT is calculated from the desired continuous mode operating frequency (fO):
-5 V CT = 7.8 x 10 1 - OUT VIN fO
)
)
A graph for selecting CT vs frequency including the effects of input voltage is given in Figure 3.
LTC1267 LTC1267-ADJ/LTC1267-ADJ5
APPLICATIO S I FOR ATIO
1400 VOUT = 5V 1200
TIMING CAPACITANCE (pF)
1000 VIN = 24V 800 600 VIN = 12V 400 200 0 0 50 100 150 FREQUENCY (kHz) 200 250
LTC1267 * F03
Figure 3. Timing Capacitor Value
As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The complete expression for operating frequency is given by:
V fO = 1 1 - OUT VIN tOFF
)
)
where: tOFF = 1.3 x 104 x CT Once the frequency has been set by CT, the inductor L must be chosen to provide no more than 0.025V/RSENSE of peak-to-peak inductor ripple current. This results in a minimum required inductor value of: LMIN = 5.1 x 105 x RSENSE x CT x VOUT As the inductor value is increased from the minimum value, the ESR requirements for the output capacitor are eased at the expense of efficiency. If too small an inductor is used, the LTC1267 may not enter Burst Mode operation and efficiency will be severely degraded at low currents. Inductor Core Selection Once the minimum value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy (MPP), or Kool M(R) cores. Actual core loss is independent of core size for a fixed inductor
Kool M is a registered trademark of Magnetics, Inc.
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value, but it is very dependent on inductance selected. As inductance increases, core losses go down but copper I2R losses increase. For additional information regarding inductor selection, please refer to the LTC1159 data sheet. Power MOSFET and Diode Selection Two external power MOSFETs must be selected for use with each section of the LTC1267: a P-channel MOSFET for the main switch, and an N-channel MOSFET for the synchronous switch. The peak-to-peak gate drive levels are set by the V CC voltage on the LTC1267. This voltage is typically 4.5V during start-up and 5V to 7V during normal operation (see EXT VCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most LTC1267 family applications. The only exceptions are applications in which EXT VCC is powered from an external supply greater than 8V, in which standard threshold MOSFETs (V GS(TH) > 4V) may be used. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logiclevel MOSFETs are limited to 30V. Selection criteria for the power MOSFETs include the onresistance RDS(ON), reverse transfer capacitance CRSS, input voltage, and maximum output current. When the LTC1267 is operating in continuous mode, the duty cycles for the two MOSFETs are given by:
V Duty Cycle = OUT VIN V - VOUT N-Channel Duty Cycle = IN VIN
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The MOSFET dissipations at maximum output current are given by:
V P-Ch PD = OUT (IMAX)2 (1 + P) RDS(ON) VIN + k (VIN)2 (IMAX) (CRSS) fO V - VOUT N-Ch PD = IN (IMAX)2 (1 + N) RDS(ON) VIN
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LTC1267 LTC1267-ADJ/LTC1267-ADJ5
APPLICATIO S I FOR ATIO
Where is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses, while the P-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V, the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The N-channel MOSFET losses are the greatest at high input voltage or during a short circuit when the N-channel duty cycle is nearly 100%. The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but = 0.007/C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET electrical characteristics. The constant k = 5 can be used for the LTC1267 to estimate the relative contributions of the two terms in the P-channel dissipation equation. The Schottky diodes D3 and D5 shown in Figure 1 only conduct during the dead-time between the conduction of the respective power MOSFETs. The sole purpose of D3 and D5 is to prevent the body diode of the N-channel MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency (although there are no other harmful effects if D3 and D5 are omitted). Therefore, D3 and D5 should be selected for a forward voltage of less than 0.6V when conducting IMAX. CIN and COUT Selection In continuous mode, the source current of the P-channel MOSFET is a square wave of duty cycle VOUT/ VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by:
CIN Required IRMS IMAX [VOUT(VIN - VOUT)]1/2 VIN
OUTPUT CAPACITANCE (F)
This formula has a maximum at VIN = 2VOUT where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours
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of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. An additional 0.1F ceramic capacitor is also required on VIN for high frequency decoupling. The selection of COUT is driven by the required Effective Series Resistance (ESR). The ESR of COUT must be less than twice the value of RSENSE for proper operation of the LTC1267: COUT Required ESR < 2RSENSE Optimum efficiency is obtained by making the ESR equal to RSENSE. As the ESR is increased up to 2RSENSE, the efficiency degrades by less than 1%. If the ESR is greater than 2RSENSE, the voltage ripple on the output capacitor will prematurely trigger Burst Mode operation, resulting in disruption of continuous mode and an efficiency hit which can be several percent. Manufacturers such as Nichicon, United Chemicon, and Sprague should be considered for high performance capacitors. In surface mount applications multiple capacitors may have to be paralleled to meet the capacitance, ESR, or RMS current handling requirements of the application. For additional information regarding capacitor selection, please refer to the LTC1159 data sheet. At low supply voltages, a minimum capacitance at COUT is needed to prevent an abnormal low frequency operating mode (see Figure 4). When COUT is made too small, the output ripple at low frequencies will be large enough to trip
1000 L = 50H RSENSE = 0.02 800 L = 25H RSENSE = 0.02 600 400 L = 50H RSENSE = 0.05 200 0 0 1 3 4 2 (VIN - VOUT) VOLTAGE (V) 5
LTC1267 * F04
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Figure 4. Minimum Suggested COUT
LTC1267 LTC1267-ADJ/LTC1267-ADJ5
APPLICATIO S I FOR ATIO
the voltage comparator. This causes Burst Mode operation to be activated when the LTC1267 would normally be in continuous operation. The effect is most pronounced with low values of RSENSE and can be improved by operating at higher frequencies with lower values of L. The output remains in regulation at all times. EXT VCC Pin Connection The LTC1267 contains an internal PNP switch connected between the EXT VCC and VCC pins. The switch closes and supplies the VCC power whenever the EXT VCC pin is higher in voltage than the 4.5V internal regulator. This allows the MOSFET driver and control power to be derived from the output during normal operation and from the internal regulator when the output is out of regulation (start-up, short circuit). Significant efficiency gain can be realized by powering VCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of Duty Cycle/Efficiency. For LTC1267, LTC1267-ADJ or LTC1267-ADJ5 this simply means connecting the EXT VCC pin directly to VOUT of the 5V regulator. The following list summarizes the four possible connections for EXT VCC: 1. EXT VCC left open. This will cause VCC to be powered only from the internal 4.5V regulator, resulting in reduced MOSFET gate drive levels and an efficiency penalty of up to 10% at high input voltages. 2. EXT VCC connected directly to highest VOUT of the two regulators. This is the normal connection for LTC1267/ LTC1267-ADJ/LTC1267-ADJ5 and provides the highest efficiency. 3. EXT VCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXT VCC to an output-derived voltage which has been boosted to greater than 4.5V. This can be done either with the inductive boost winding shown in Figure 5a or the capacitive charge pump shown in Figure 5b. The charge pump has the advantage of simple magnetics and generally provides the highest efficiency at the expense of a slightly higher parts count.
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VIN
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+
EXT VCC VIN P-CH CIN L 1:1 PGATE 3 PDRIVE 3 LTC1267 NGATE 3 PGND3 N-CH
1N4148
+
*
1F RSENSE VOUT 3.3V
*
+
COUT
LTC1267 * F05A
Figure 5a. Inductive Boost Circuit for EXT VCC
VIN
+ +
1F CIN BAT 85
BAT 85 0.22F
EXT VCC
VIN P-CH
PGATE 3 PDRIVE 3 LTC1267 NGATE 3 PGND3
VN2222LL L RSENSE BAT 85 VOUT 3.3V COUT
LTC1267 * F05B
N-CH
+
Figure 5b. Capacitive Charge Pump for EXT VCC
4. EXT VCC connected to an external supply. If an external supply is available in the 5V to 10V range it may be used to power EXT VCC providing it is compatible with the MOSFET gate drive requirements. When driving standard threshold MOSFETs, the external supply must always be present during operation to prevent MOSFET failure due to insufficient gate drive. Under the condition that EXT VCC is connected to VOUT1 which is greater than 5.5V, to power down the whole regulator, both the pins MSHDN and SHDN1 have to be pulled high. If SHDN1 is left floating or grounded the EXT VCC may self-power from VOUT1, preventing complete shutdown. LTC1267 Adjustable Applications When an output voltage other than 3.3V or 5V is required, the LTC1267-ADJ and LTC1267-ADJ5 adjustable versions are used with an external resistive divider from VOUT to the VFB1, 2 pins. This is shown in Figure 6. The regulated voltage is determined by:
VOUT = 1 + R2 1.25V R1
))
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LTC1267 LTC1267-ADJ/LTC1267-ADJ5
APPLICATIO S I FOR ATIO
The VFB1, 2 pin is extremely sensitive to pickup from the inductor switching node. Care should be taken to isolate the feedback network from the inductor and a 100pF capacitor should be connected between the VFB1, 2 and SGND pins next to the package. The circuit in Figure 6 cannot be used to regulate a VOUT which is greater than the maximum voltage allowed on the LTC1267 EXT V CC pin (10V). In applications with VOUT > 10V, RSENSE must be moved to the ground side of the output capacitor and load. This operates the current sense comparator at 0V common mode, increasing the off-time approximately 40% and requiring the use of a smaller timing capacitor CT.
RSENSE VFB1, 2 100pF SGND
LTC1267 * F06
R2
+
R1
VOUT COUT
Figure 6. LTC1267-ADJ/LTC1267-ADJ5 External Feedback Network
Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc., are the individual losses as a percentage of input power. (For high efficiency circuits, only small errors are incurred by expressing losses as a percentage of output power.) Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1267 circuits: 1. 2. 3. 4. LTC1267 VIN current LTC1267 VCC current I2R losses P-channel transition losses
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1. LTC1267 VIN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. VIN currents results in a small (<1%) loss which increases with VIN . 2. LTC1267 VCC current is the sum of the MOSFET driver and control circuits currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VCC to ground. The resulting dQ/dt is a current out of VCC which is typically much larger than the control circuit current. In continuous mode IGATECHG fO(QP +QN), where QP and QN are the gate charges of the two MOSFETs. By powering EXT VCC from an output-derived source, the additional VIN current resulting from the driver and control currents will be scaled by a factor of Duty Cycle/ Efficiency. For example, in a 20V to 5V application, 10mA of VCC current results in approximately 3mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3. I2R losses are easily predicted from the DC resistances of the MOSFET, inductor, and current shunt. In continuous mode all the output current flows through L and RSENSE, but is "chopped" between the P-channel and Nchannel MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and RSENSE to obtain I2R losses. For example, if each RDS(ON) = 0.1, RL = 0.15, and RSENSE = 0.05, then the total resistance is 0.3. This results in losses ranging from 3% to 12% as the output current increases from 0.5A to 2A. I2R losses cause the efficiency to roll off at high output currents. 4. Transition losses apply only to the P-channel MOSFET and only when operating at high input voltages (typically 20V or greater). Transition losses can be estimated from: Transition Loss 5 x VIN2 x IMAX x CRSS x fO Other losses including CIN and COUT ESR dissipative losses, Schottky conduction losses during dead-time,
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LTC1267 LTC1267-ADJ/LTC1267-ADJ5
APPLICATIO S I FOR ATIO
and inductor core losses, generally account for less than 2% total additional loss. Auxiliary Windings--Suppressing Burst Mode Operation The LTC1267 synchronous switch removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. With synchronous switching, auxiliary outputs may be loaded without regard to the primary output load, providing that the loop remains in continuous mode operation. Burst Mode operation can be suppressed at low output currents with a simple external network which cancels the 25mV minimum current comparator threshold. This technique is also useful for eliminating audible noise from certain types of inductors in high current (IOUT > 5A) applications when they are lightly loaded. An external offset is put in series with the Sense - pin to subtract from the built-in 25mV offset. An example of this technique is shown in Figure 7. Two 100 resistors are inserted in series with the sense leads from the sense resistor.
L R2 100 1000pF R1 100 RSENSE
SENSE + LTC1267 SENSE - R3
LTC1267 * F07
Figure 7. Suppressing Burst Mode Operation
With the addition of R3 a current is generated through R1 causing an offset of:
VOFFSET = VOUT
)R1R1R3) +
If VOFFSET > 25mV, the built-in offset will be cancelled and Burst Mode operation is prevented from occurring. Since VOFFSET is constant, the maximum load current is also decreased by the same offset. Thus, to get back to the same IMAX, the value of the sense resistor must be reduced:
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RSENSE 75 m IMAX
To prevent noise spikes from erroneously tripping the current comparator, a 1000pF capacitor is needed across Sense+ and Sense- pins. Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1267. These items are also illustrated graphically in the layout diagram of Figure 8. In general each block should be self-contained with little cross coupling for best performance. Check the following in your layout: 1. Are the signal and power grounds segregated? The LTC1267 signal ground must return to the (-) plate of COUT. The power ground returns to the source of the N-channel MOSFET, anode of the Schottky diode, and (-) plate of CIN, which should have as short lead lengths as possible. 2. Does the LTC1267 Sense - pin connect to a point close to RSENSE and the (+) plate of COUT? In adjustable applications the resistive divider R1 and R2 must be connected between the (+) plate of COUT and signal ground. 3. Are the Sense - and Sense + leads routed together with minimum PC trace spacing? The 1000pF capacitor between the two Sense pins should be as close as possible to the LTC1267. Up to 100 may be placed in series with each Sense lead to help decouple the Sense pins. However, when these resistors are used the capacitor should be no larger than 1000pF. 4. Does the (+) plate of CIN connect to the source of the P-channel MOSFET as closely as possible? An additional 0.1F ceramic capacitor between VIN and power ground may be required in some applications. 5. Is the VCC decoupling capacitor connected closely between the VCC pins of the LTC1267 and power ground? This capacitor carries the MOSFET driver peak currents.
+
COUT
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LTC1267 LTC1267-ADJ/LTC1267-ADJ5
APPLICATIO S I FOR ATIO
1N4148 1 2 0.15F P-CH N-CH 0.1F 3 4 5 6 CIN3 L3 1F 7
VCC VIN CAP3 PGATE 3 PDRIVE 3 NGATE 3 PGND3
D3
+
8 VCC3 9 LTC1267 CT3 ITHR3 SGND3 SHDN3 SENSE - 3 SENSE + 3
1k RSENSE3 COUT3 CT3
3300pF 10 11
SENSE + 5 SENSE - 5 CT5 ITHR5
18 17 16 3300pF 15 1k
LTC1267 * F08
SHDN3
12 13
1000pF VOUT5 BOLD LINES INDICATE HIGH CURRENT PATHS
1000pF VOUT3
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Figure 8. LTC1267 Layout Diagram
6. In adjustable versions, the feedback pin is very sensitive to pickup from the switch node. Care must be taken to isolate VFB1, 2 from possible capacitive coupling of the inductor switch signal. 7. Are MSHDN and SHDN1, 3, 5 actively pulled to ground during normal operation? These shutdown pins are high impedance and must not be allowed to float. Troubleshooting Hints Since efficiency is critical to LTC1267 applications, it is very important to verify that the circuit is functioning correctly in both continuous and Burst Mode operation. The waveform to monitor is the voltage on the CT pin. In continuous mode (ILOAD > IBURST) the voltage on the CT pin should be a sawtooth with a 0.9VP-P swing. This voltage should never dip below 2V as shown in Figure 9a. When load currents are low (ILOAD < IBURST) Burst Mode operation occurs. The voltage on the CT pin now falls to ground for periods of time as shown in Figure 9b.
If the CT is observed falling to ground at high output currents, it indicates poor decoupling or improper grounding. Refer to the Board Layout Checklist. Inductor current should also be monitored. Look to verify that the peak-to-peak ripple current in continuous mode operation is approximately the same as in Burst Mode operation.
3.3V
(a) CONTINUOUS MODE OPERATION 3.3V
(b) Burst Mode OPERATION
Figure 9. CT Waveforms
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VIN EXT VCC MSHDN CAP5 PGATE 5 PDRIVE 5 NGATE 5 PGND5 VCC5 SGND5 SHDN5 28 27 26 25 24 23 22 21 20 19 SHDN5 CT5 CIN5 0.1F 1N4148 MSHDN 0.15F P-CH N-CH
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+
+
D5 L5
+
1F
COUT5 RSENSE5
+
0V
0V
LTC1267 * F09
LTC1267 LTC1267-ADJ/LTC1267-ADJ5
TYPICAL APPLICATIONS N
LTC1267-ADJ Dual Regulator with 3.6V/2.5A and 5V/2A Outputs
VIN 5.4V to 25V
+
CIN1 100F 50V
+
3.3F P-CH Si9435DY 1N4148 7 4 5 13 1000pF 12 11 SENSE - 1 SHDN1 NGATE 1 VFB1 14 100pF VCC1 PGATE 1 PDRIVE 1 SENSE + 1
VOUT1 3.6V 2.5A
RSENSE1 0.04
L1 20H
0.1F
D1 MBRS140T3 COUT1 220F 10V x2
+
R2 100k 1% R1 52.3k 1%
N-CH Si9410DY
RSENSE1: KRL SL-1R040J L1: COILTRONICS CTX20-4
LTC1267-ADJ5 Dual Regulator with 3.45V/2.5A and 5V/2A Outputs
VIN 5.4V to 25V
+
CIN1 100F 50V
+
3.3F P-CH Si9435DY 1N4148 7 4 5 13 1000pF 12 11 SENSE - 1 SHDN1 NGATE 1 VFB1 14 100pF VCC1 PGATE 1 PDRIVE 1 SENSE + 1
VOUT1 3.45V 2.5A
RSENSE1 0.04
L1 20H
0.1F
D1 MBRS140T3 COUT1 220F 10V x2
+
R2 100k 1% R1 56.2k 1%
N-CH Si9410DY
RSENSE1: KRL SL-1R040J L1: COILTRONICS CTX20-4
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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6 6
+
0.15F 3 CAP1 1 VCC 2 VIN 0.15F 1N4148 27 26 28 21 PGATE 2 PDRIVE 2 SENSE + 2 LTC1267-ADJ SENSE - 2 17 23 22 N-CH Si9410DY D2 MBRS140T3 25 24 18 1000pF 0.1F P-CH Si9435DY L2 33H RSENSE2 0.05
CIN2 100F 50V
+
3.3F
MSHDN CAP2 EXT VCC VCC2
VOUT2 5V 2A
NGATE 2 PGND2 SGND1 CT1 10 8 ITH1 9 ITH2 15 CT2 16 SGND2 20 100pF VFB2 19
+
R2 150k 1% R1 49.9k 1%
CC1 CC2 CT2 CT1 270pF 3300pF 3300pF 270pF RC1 1k RC2 1k
COUT2 220F 10V x2
MSHDN, SHDN1 0V = NORMAL, >2V = SHDN
RSENSE2: KRL SL-1R050J L2: COILTRONICS CTX33-4
LTC1267 * F010
+
0.15F 3 CAP1 1 VCC 2 VIN 0.15F 1N4148 27 26 28 21 PGATE 5 PDRIVE 5 SENSE + 5 LTC1267-ADJ5 SENSE - 5 SHDN5 NGATE 5 SGND1 CT1 10 8 ITH1 9 ITH5 15 CT5 16 SGND5 PGND 20 22 17 19 23 N-CH Si9410DY D2 MBRS140T3 25 24 18 1000pF 0.1F P-CH Si9435DY L2 33H RSENSE2 0.05
CIN2 100F 50V
+
3.3F
MSHDN CAP5 EXT VCC VCC5
VOUT2 5V 2A
+
CC1 CC5 CT5 CT1 270pF 3300pF 3300pF 270pF RC1 1k RC5 1k RSENSE2: KRL SL-1R050J L2: COILTRONICS CTX33-4
LTC1267 * F011
COUT2 220F 10V x2
MSHDN, SHDN1, SHDN5 0V = NORMAL, >2V = SHDN
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LTC1267 LTC1267-ADJ/LTC1267-ADJ5
PACKAGE DESCRIPTIO U
Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP
0.397 - 0.407* (10.07 - 10.33) 0.205 - 0.212* (5.20 - 5.38) 0.068 - 0.078 (1.73 - 1.99) 28 27 26 25 24 23 22 21 20 19 18 17 16 15
0 - 8 0.301 - 0.311 (7.65 - 7.90) 0.010 - 0.015 (0.25 - 0.38) 0.002 - 0.008 (0.05 - 0.21)
0.005 - 0.009 (0.13 - 0.22)
0.022 - 0.037 (0.55 - 0.95)
0.0256 (0.65) BSC
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm). 1 2 3 4 5 6 7 8 9 10 11 12 13 14
28SSOP 0694
RELATED PARTS
PART NUMBER LTC1142 LTC1143 LTC1147 LTC1148 LTC1149 LTC1159 LTC1174 LTC1265 LTC1266 LTC1574 DESCRIPTION Dual Step-Down Switching Regulator Controller Dual Step-Down Switching Regulator Controller Step-Down Switching Regulator Controller Step-Down Switching Regulator Controller Step-Down Switching Regulator Controller Step-Down Switching Regulator Controller Step-Down Switching Regulator with Internal 0.5A Switch Step-Down Switching Regulator with Internal 1A Switch Step-Up/Down Switching Regulator Controller Step-Down Switching Regulator with Internal 0.5A Switch and Schottky Diode COMMENTS Dual Version of LTC1148 Dual Version of LTC1147 Nonsynchronous, 8-Pin, VIN 16V Synchronous, VIN 20V Synchronous, VIN 48V, for Standard Threshold FETs Synchronous, VIN 40V, for Logic Level FETs VIN 18.5V, Comparator/Low Battery Detector VIN 13V, Comparator/Low Battery Detector Synchronous N- or P-Channel FETs, Comparator/Low Battery Detector VIN 18.5V, Comparator
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
LT/GP 0695 10K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1995

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